The present invention relates generally to electronic circuits and, more particularly, to programmable gain amplifiers.
FIG. 1 shows a schematic diagram of a conventional, single-ended programmable gain amplifier (PGA) (a.k.a. variable gain amplifier or VGA) 100, which receives analog input signal Vin and generates amplified analog output signal Vout. The gain of the PGA 100 is programmably set by closing one or both of input switches S1 and S2 to select a particular level for the input resistance applied to operational amplifier (op amp) 102 based on one or both of input resistors Ri1 and Ri2, and closing one or both of feedback switches S3 and S4 to select a particular level for the feedback resistance applied to the op amp 102 based on one or both of feedback resistors Rf1 and Rf2.
To configure the PGA 100 for normal operating mode, switch Sc is opened and switch Scb is closed such that input signal Vin is applied via the input resistance to the op amp 102. To configure the PGA 100 for calibration mode, switch Scb is open and switch Sc is closed such that the amplifier input is tied to ground through the input resistance. In this calibration mode configuration, the amplifier output signal Vout indicates the DC offset of the PGA 100. This DC offset value can be digitized, e.g., by an analog-to-digital converter (ADC) (not shown in FIG. 1) and retained, e.g., in the memory of a digital signal processor (DSP) (not shown in FIG. 1) and used by the DSP during the normal operating mode, e.g., by subtracting the stored digital DC offset value from the digitized output of the ADC corresponding to the amplifier output signal Vout.
Each additional series switch in the PGA 100 adversely affects its linearity and therefore the linearity of a system containing the PGA 100.